Protocol aware digital channel apparatus

ABSTRACT

In one embodiment, provided is a protocol specific circuit for simulating a functional operational environment into which a device-under-test is placed for functional testing. The protocol specific circuit includes a protocol aware circuit constructed to receive a non-deterministic signal communicated by a device-under-test and to control a transfer of the test stimulus signal to the device-under-test in response to the a non-deterministic signal.

RELATED PATENT APPLICATIONS

The present application is related to U.S. patent application Ser. No.______, filed on a same date as the present application, entitled AMETHOD FOR TESTING IN A RECONFIGURABLE TESTER; by George W. Conner,assigned to the same assignee as the present invention, and isincorporated herein by reference.

BACKGROUND

Automated stored pattern functional testing affords a critical step inthe production of integrated circuit (IC) devices to provide parametricand operational characterization of the devices. An automatic testequipment system includes test circuitry that is connected to a controlcomputer. The control computer provides a user interface that acceptsand stores functional test pattern data for activating the testcircuitry to provide stimulus signals to a device-under-test andreceives the response signals from the device-under-test. The responsesignals are evaluated to determine the parametric and operationalcharacterization of the integrated circuit devices.

The device-under-test (DUT) is mounted on a device interface board orDIB, which provides the physical interface from/to the pin electronics.The pin electronics circuitry is the electrical interface thatprovides/receives the electrical test stimulus/response signals to/fromthe device-under-test via the DIB. The test stimulus signals from thetest circuitry are supplied through pin electronics to thedevice-under-test via the DIB. The test response signals from thedevice-under-test are transferred through DIB to the pin electronics andon to the test circuitry. The test stimulus signals and the testresponse signals are correlated by the test circuitry to determinewhether the device-under-test has passed or failed the test.

The stimulus signals generated by the test circuitry include datasignals and clock signals to synchronize the stimulus input. Theeffectiveness of the test depends on the accurate placement of thesesignals relative to one another. For example, several different signals,such as, clock, data, and enable signals are coordinated and triggeredat appropriate times to ensure that meaningful data is acquired duringthe test process. Inaccuracy of clock and data signal edge placementwill result in false test results. As the operating speed of devices tobe tested increases, the margins of error for edge placement accuracydecreases.

A system-on-a-chip (SOC) provides multiple digital and analog integratedcircuit functions incorporated on the same semiconductor substrate. Anexample of an SOC is a cellular telephone that incorporates not onlycellular telephone receiving, processing, and transmitting functions,but also photographic and video processing functions, audio digitalsignal processing and semiconductor memory circuits. Presently, in mostSOC testing, the individual functions of an SOC are tested separately inmultiple testing methods, such as by SCAN testing, Built-In-Self-Test(BIST), and functional testing. System Level Test typically employscustom circuitry and is generally only used for high average sellingprice low mix devices, such as microprocessors. A final system leveltest may be implemented on customized test apparatus createdspecifically for the testing of specific SOC devices such asmicroprocessors. Although it would be desirable to perform a SystemLevel Test for other SOC devices, building custom functional testapparatuses for low average selling price SOCs is not cost effective.

A difficulty in testing SOCs with automatic test circuitry is that theparametric and individual functional testing with the automatic testcircuitry is a deterministic test operation. The test stimulus signalsare applied with certain timing and structure, and the test responsesignals are expected to have a particular timing and structure. If thetest response signals do not match the expected timing and structure forthe given parameters, the SOC device-under-test is determined to havefailed. The functions of the SOC device may operate with differingtiming and clocking specifications and may in fact operateasynchronously. An SOC device may be operational when the response testsignals indicate otherwise, when the asynchronicity of the communicatingfunctions cause the test response signals to appear incorrect.

There have been attempts within present automatic test equipment systemsto simulate the operating conditions of an SOC device-under-test.Because of the nondeterministic function of the asynchronouscommunication between circuit functions, the normal operatingenvironment of the functions can not be accurately recreated for the SOCdevice-under-test. Present automatic test equipment environments lackthe ability to easily and accurately provide the nondeterministicelectrical and timing conditions of the normal operating environment ofthe SOC device-under-test. This lack of the nondeterministic electricaland timing conditions within automatic test equipment systems, furtherdo not measure the margin of error for an SOC device-under-test withregard to its tolerance under varying operational conditions that may bepresent in its normal operational environment.

Therefore, what is needed is an automatic test equipment system capableof providing deterministic and nondeterministic test stimulus signals.The nondeterministic test stimulus signals provide the electrical andtiming protocol of the normal operating environment of thedevice-under-test such that the automatic test equipment system respondsto test response signals of the device-under-test as though thedevice-under-test is operating in its normal environment.

SUMMARY

In one embodiment, provided is a protocol specific circuit forsimulating a functional operational environment into which adevice-under-test is placed for functional testing. The protocolspecific circuit includes a protocol aware circuit constructed toreceive a non-deterministic signal communicated by a device-under-testand to control a transfer of the test stimulus signal to thedevice-under-test in response to the a non-deterministic signal.

In some embodiments the protocol specific circuit is constructed toreceive the non-deterministic signal communicated by a protocol specificdevice-under-test via pin electronics and to control transfer of thetest stimulus signal from a test signal generator to thedevice-under-test. In some embodiments, the protocol specific circuit isconstructed to store the test stimulus signal from the test signalgenerator in a stimulus signal storage device, such as a FIFO. In someembodiments, the protocol specific circuit is constructed to store thenon-deterministic signal in a response signal storage device, such as aFIFO.

In various embodiments, the protocol specific circuit is constructed toextract the non-deterministic signal from the response signal storagedevice for comparison by a failure processor with an expected responsesignal, and determine an operational condition of the device-under-test.

In some embodiments, the protocol specific circuit is constructed formounting in automated test equipment to allow the automatic testequipment to simulate a functional operational environment into whichthe device-under-test is placed for functional testing and the protocolaware circuit interprets the non-deterministic signal to determine asynchronization time and a latency time for transmission of the teststimulus signal.

In another embodiment, provided is a protocol specific circuit having aconfigurable protocol aware circuit capable of being preconfigured tocommunicate test stimulus signal between a test signal generator and aspecific device-under-test via pin electronics in response to anon-deterministic signal from the device-under-test.

In some embodiments, the protocol specific circuit is preconfigured torespond to a specific device-under-test in response to thenon-deterministic signal having an asynchronously occurring signal fromthe device-under-test. In some embodiments, the protocol specificcircuit includes a protocol decoder, which may be programmable, such asa field programmable gate array. In some embodiments, the fieldprogrammable gate array includes the protocol aware circuit coupled to amemory device, such as a FIFO.

In some embodiments, the protocol specific circuit includes a memorybuffer configured to store the test stimulus signal generated by thetest signal generator and to provide the stored test stimulus signal viathe pin electronics, to the device-under-test in response to anon-deterministic signal from the device-under-test. The memory buffermay be a FIFO.

In various embodiments, the protocol specific circuit includes apass-through circuit coupled in parallel with the protocol aware forreceiving deterministic signals from the device-under-test.

In another embodiment, provided is test equipment including a protocolaware channel for testing a device-under-test, the protocol awarechannel includes a protocol specific circuit coupled between a testsignal generator and a pin electronics circuit, the protocol specificcircuit is constructed to be capable of being preconfigured to respondto the protocol specific device-under-test in response to anon-deterministic signal from the device-under-test.

In some embodiments, the protocol specific circuit includes a protocoldecoder. In some embodiments, the protocol specific circuit includes afield programmable gate array, which may include the protocol awarecircuit coupled to a memory device. In some embodiments, the protocolspecific circuit includes a memory buffer configured to store the atleast one test stimulus signal generated by the test signal generatorand to provide the stored test stimulus signal via the pin electronics,to the device-under-test in response to a non-deterministic signal fromthe device-under-test. In some embodiments, the protocol specificcircuit includes a pass-through circuit coupled in parallel with theprotocol aware for receiving deterministic signals from thedevice-under-test.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram of an integrated circuit device structurehaving a non-deterministic behavior.

FIG. 2 is a block diagram of an embodiment of a protocol specificcircuit within an automatic test equipment system.

FIG. 3 is a block diagram of another embodiment an automatic testequipment system incorporating one embodiment of a protocol specificcircuit.

FIG. 4 is a block diagram of an automatic test equipment systemincorporating multiple instances of one of the embodiments of theprotocol specific circuits.

FIGS. 5 a and 5 b are flow diagrams of a method for simulating within anautomatic test system a functional operational environment into which adevice-under-test is placed for functional testing.

FIG. 6 is a block diagram illustrating a Double Data Rate Random AccessMemory Controller protocol, which some embodiments of the protocolspecific circuit may simulate.

FIG. 7 is a block diagram of one embodiment of the protocol specificcircuits within an automatic test equipment system configured tosimulate the Double Data Rate Random Access Memory Controller protocolof FIG. 6.

FIGS. 8 and 9 are plots respectively of the read and write timing of theDouble Data Rate Random Access Memory Controller protocol as generatedby one of the embodiments of the protocol specific circuits within anautomatic test equipment system of FIG. 5.

DESCRIPTION

As described above, in recent years stored pattern functional testinghas run into increasing difficulties with devices that do not behavedeterministically. Presently, the level of integration and complexity ofsemiconductor processing is allowing for integrated circuit chips toeffectively be a complete “system-on-a-chip” (SOC). A system-on-a-chipintegrates all the functional circuit elements of a computer or otherelectronic system into a single integrated circuit (chip). Theseintegrated circuit elements may be any combination of digital circuits,analog circuits, random access memory, mixed analog and digital signalcircuits, and often include radio-frequency functions. Referring to FIG.1, the SOC devices has multiple intellectual property (IP) integratedcircuit element blocks 105 a and 105 b. In the present illustration,only two of the IP blocks 105 a and 105 b are shown for ease ofexplanation, but it is apparent to one skilled in the art that largenumbers of complex IP blocks are integrated on an SOC device 100. Inthis illustration, the two IP blocks communicate through an asynchronousinterface 110.

When the SOC device 100 is tested to determine parametric and functionaloperation, the SOC device 100 is placed in a device-under-test fixture125 and connected through pin electronics to the automated testequipment system 120. The pin electronics provides the electricalinterface between the device-under-test and automated test equipmentsystem 120. The automated test equipment system 120 generates,transmits, receives, and evaluates sets of test patterns 130 and 135 todetermine the parametric and functional operation of the SOC device 100.

Each of the IP blocks 105 a and 105 b generally has its own clock andtiming domains 115 a and 115 b that are generally not synchronized. Thetest stimulus signal 132 may cause the IP block 105 a to communicatewith the IP block 105 b, which will cause the test response signal 139of the IP block 105 b to be incorrect. Similarly, the test stimulussignal 137 may cause the IP block 105 b to communicate with the IP block105 a, which will cause the test response signal 134 of the IP block 105a to be incorrect. This nondeterministic communication will vary betweenSOC devices 100 and within the same SOC device 100 at different voltagesand temperatures.

The current generation automated test equipment systems 120 are capableof providing the test stimulus signals 132 to the IP block 105 a and thetest stimulus signals 137 to the IP blocks 105 b and receiving the testresponse signals 134 from the IP blocks 105 a and the test responsesignals 139 from the IP blocks 105 b. In this case the testing isdeterministic in that the test response signals 134 and 139 matchcertain structures and timing to be valid. Any communication between theIP blocks 105 a and 105 b is curtailed and the interaction is notverified.

The current generation automated test equipment systems 120 have verylimited capability to deal with non-deterministic SOC devices 100 otherthan provide to certain latency factors. This causes the test engineersignificant problems, in that the first prototyped devices, more thanlikely, will not work when the test stimulus signals 132 and 137 are thesimulation vectors used in the design verification. A series of trialand error loops ensues in which the test engineer tries to move vectorsaround until he finds a passing arrangement. Due to the large volume ofdata involved and the need to re-simulate every trial, each loop maytake days, the net result being months added to the test and evaluationphase of a new SOC device.

In all probability, the test engineer may never find a single set oftest stimulus signals 132 and 137 that works for all devices and may befaced with supporting many sets of the test stimulus signals 132 and137. In this situation, if any one passes, the device is deemed good.This causes a test time penalty for having to support many patterns andthere is a very real possibility that not all possible good patternswill have been discovered, thus creating an adverse yield impact.

In this situation, months can be added to time to market and deviceyields may be reduced. Some organizations have chosen to address theinability to cope with the nondeterministic functioning of the IP blocks105 a and 105 b within a SOC device 100 by moving away from functionaltesting on an automated test equipment system 120 entirely using someform of structural test. While structural test is a necessary ingredientof a successful test plan, it is not sufficient in the present era ofsemiconductor processing with current geometries.

To solve the problem of device non-determinism to permit use ofautomated test equipment systems 120, an embodiment of an automated testequipment systems 120 includes a protocol specific circuit forsimulating a functional operational environment into which an SOC device100 to be tested is placed for functional testing. The protocol specificcircuit is aware of the protocol that the IP blocks 105 a and 105 b arecommunicating. The basic problem caused by non-determinism is that whilethe SOC device 100 may end up doing the same thing each time, it doesn'tnecessarily do it the same way each time. It may want data presented acycle earlier or later than the last time it ran. An obvious solution tothis behavior is, rather than simply spewing data at the SOC device 100,to wait until the device is ready for it. In order to wait until the SOCdevice 100 is ready, however, the automated test equipment system 120,in some sense, understands the function of the test response signals 134and 139 from the SOC device 100.

To keep up with increasing SOC device 100 speeds, current automated testequipment systems 120 have increased the pipeline depth of the patterngenerators. This has allowed the use of low cost CMOS technology for allbut the last few transistors in the automated test equipment system 120channel, yet has permitted speeds in excess of 6.4 Gbps, with patternsthat approach Gigabit depth, to be achieved. A side effect of this trendis that if the pattern flow of the automated test equipment system 120needs to be changed in order to respond to the device, there may be alatency of several microseconds to clear the pipeline.

A protocol aware circuit is placed as close as possible to thedevice-under-test fixture 125 and thus to the SOC device 100 to receivethe non-deterministic test response signals 134 and 139 communicated bya SOC device 100 through the device-under-test fixture 125. The protocolaware circuit controls a transfer of test stimulus signals 132 and 137to the SOC device 100 in response to non-deterministic test stimulussignals 132 and 137.

Refer now to FIG. 2 for a detailed explanation of the protocol specificcircuit 205 within an embodiment of an automated test equipment system200. A data generator 225 creates the test stimulus signals from thetest pattern commands stored in the Dynamic Random Access Memory (DRAM)220. The test stimulus signals are transferred to the source memory 230of the protocol specific circuit 205 which acts to speed match the teststimulus signals to the specifications of the SOC device-under-test 215.

Ideally, the source memory 230 is a random access memory (RAM) thatallows the random access of the test stimulus signals. In a true RAMmode, it may not be necessary to provide test vectors for operation, theDUT can write data in and then read the data out when requested. The RAMtypically works for speeds below around 1 GHz and port pin counts up to128 pins, in current technology. However, because of the performancerequirements of the SOC device-under-test 215 with faster speeds orwider busses, the source memory 230 may be a First-In-First-Out (FIFO)memory where the test stimulus signals are ordered and transferred atthe required speed. It should be noted, that either/both the FIFO andtrue RAM mode (in addition to other protocols) are supported in variousembodiments.

The output of the source memory 230 is sent to a transmission buffercircuit 235 that amplifies and conditions the test stimulus signals fortransfer on the physical interconnections 237 and 239 to the pinelectronics 210 a and 210 b. The pin electronics 210 a and 210 bprovides the electrical interface 202 and 204 between the SOCdevice-under-test 215 and the automated test equipment system 200. Innormal deterministic operation, the test stimulus signals aretransferred at determined times and with a determined structure based onthe test vectors stored in the DRAM 220. The test stimulus signals areapplied to the desired IP block 217 i of the IP blocks 217 a, 217 b, . .. , 217 i, . . . and 217 n that populate the SOC device-under-test 215.

In the deterministic operation mode, the IP block 217 i responds withthe test response signals on the interface 204 to the pin electronics210 a and 210 b. The pin electronics 210 a and 210 b then transfer thetest response signals on the interface 252 to the receiver 250. Thereceiver 250 amplifies and conditions the test response signals andtransfers them to the capture memory 255. The capture memory 255 acts tobuffer the test response signals for transfer from the protocol specificcircuit 205 to the failure processor 260. The capture memory 255 isgenerally a FIFO memory where the ordered test response signals aretransferred at the required speed.

The failure processor 260 receives the test response signals from thecapture memory 255 and the test stimulus signals from the data generator225 for comparison. Any of the test response signals that are incorrectare logged to the DRAM 220 for further analysis.

The deterministic operation mode of the automated test equipment system200 as described provides the deterministic operation as in theautomated test equipment systems of the prior art. The protocol specificcircuit 205 has mode selection circuits 240 and 265 that switch from thedeterministic operation mode to the non-deterministic operation modebased on the state of the protocol aware selection signal 245. For thedeterministic operation mode, as just described, the protocol awareselection signal 245 is set such that the mode selection circuit 240 hasthe control of the source memory 230 from the data generator 225 and themode selection circuit 265 has the control of the capture memory 255from the failure processor 260. In the non-deterministic operation mode,the protocol aware selection signal 245 is set such that the control ofthe source memory 230, and the capture memory 255 is from a protocolaware engine 270.

The protocol aware engine 270 may be a reconfigurable integrated circuitsuch as for example a field programmable gate array (FPGA) that isreconfigured to accept a protocol from the SOC device-under-test 215,decode the protocol into a command, address, and/or data. From thereceived command, address, timing, and/or data, the protocol awareengine 270 determines the structure and the timing of the test stimulussignals that are to be transferred from the source memory 230 to the IPblock 217 i through the transmitter 235 and the pin electronics 210 aand 210 b. For example, if the automated test equipment system 200 is tostimulate random access memory (RAM) and the IP block 217 i of the SOCdevice-under-test 215 is a memory controller, the memory controller 217i sends test response signals that when decoded are the address,command, control, timing, and data for a RAM. The protocol aware engine270 receives test response signals and decodes the test response signalsinto the address, command, control, timing, and data. The protocol awareengine 270 determines the structure and timing of the test stimulussignals that are to be supplied to the IP block 217 i of the SOCdevice-under-test 215. In the case of a read command of the RAM, theprotocol aware engine 270 determines the read latency timing and thestructure of the data to be transferred and commands the source memory230 to transfer the test stimulus signals accordingly. In the case ofthe write, the protocol aware engine 270 decodes the address andcommands from the capture memory 255 to store the written data. Theprotocol aware engine 270 also initiates any response acknowledging thewrite as a test stimulus signal to the IP block 217 i. In this action,any of the IP blocks 217 a, 217 b, . . . , and 217 n that are beingtested will interact with the IP block 217 i in a functionally correctmanner as though the SOC device-under-test 215 were in its standardoperating environment.

It should be noted that the source memory 230 and the capture memory 255could be random access memories such as a static RAM or dynamic RAM.However, in simulating the operating environment of a high performanceSOC device-under-test 215, the source memory 230 and the capture memory255 may be First-In-First-Out (FIFO) memories. The FIFO memories bytheir nature allow faster transfer and receipt of the test stimulussignals than do the static and dynamic RAM's.

To assure appropriate synchronicity of the transfer of the test responsesignals, the protocol aware engine 270 may optionally be clocked by theDevice-Under-Test clock 280 during the non-deterministic mode ofoperation and the automated test equipment system 200 clock 285 fordeterministic operation. The automated test equipment system 200 clock285 may be optionally selected when automated test equipment system 200is initiating the non-deterministic operation, as a master, and is thusthe source of the clock. The optional multiplexer 275 is controlled bythe aware selection signal 245 to control the operational mode of theprotocol aware engine 270 between the deterministic and thenon-deterministic modes.

The protocols that various embodiments of the automated test equipmentsystem 200 may be required to simulate fall generally into two broadcategories. In a first example, the SOC device-under-test 215 controlsthe interface between automated test equipment system 200 and the SOCdevice-under-test 215. In a second example, the automated test equipmentsystem 200 controls the interface between the SOC device-under-test 215and the automated test equipment system 200. In the first example, theSOC device-under-test 215 communicates the non-deterministic signals andthe automated test equipment system 200 responds. In the second example,the automated test equipment system 200 sends the test stimulus signalswith the appropriate protocol structure and timing to the SOCdevice-under-test 215 and the SOC device-under-test 215 responds withthe non-deterministic test response signals that are decoded, asdescribed above. In either example, the automated test equipmentrecognizes a non-deterministic response signal from the SOCdevice-under-test and response.

Refer now to FIG. 3 for a detailed explanation of another embodiment ofa protocol specific circuit 305 within an automated test equipmentsystem 300. The protocol specific circuit 305 has a channel functiongenerator 325 that creates the test stimulus signals from the testpattern commands stored in the Dynamic Random Access Memory (DRAM) 320.The channel function generator 325 communicates with the memorycontroller 360 to retrieve the test pattern commands from the DRAM 320.The memory controller 360 generates the necessary address, timing, andcommand signals for accessing the test pattern commands from the DRAM320. The memory control 360 receives the test pattern commands andtransfers them to the channel function generator 325. The test patterncommands are then decoded to form the test stimulus signals. The teststimulus signals are then transferred to the through the mode selectioncircuits 340 and 365 to the transmission buffer circuit 335. Thetransmission buffer circuit 335 amplifies and conditions the teststimulus signals for transfer on the physical interconnections 337 and339 to the pin electronics 310 a and 310 b. The pin electronics 310 aand 310 b provides the electrical interface 302 and 304 between the SOCdevice-under-test 315 and the automated test equipment system 300. Innormal deterministic operation, the test stimulus signals aretransferred at determined times and with a determined structure based onthe test vectors stored in the DRAM 320. The test stimulus signals areapplied to the desired IP block 317 i of the IP blocks 317 a, 317 b, . .. , 317 i, . . . and 317 n that populate the SOC device-under-test 315.

In the deterministic operation mode, the IP block 317 i responds withthe test response signals on the interface 304 to the pin electronics310 a and 310 b. The pin electronics 310 a and 310 b then transfer thetest response signals on the interface 352 to the receiver 350. Thereceiver 350 amplifies and conditions the test response signals andtransfers them to the capture memory 355. The capture memory 355 acts tobuffer the test response signals for transfer to the memory controller360 and the channel function generator. The capture memory 355 isgenerally a FIFO memory where the ordered test response signals aretransferred at the speed dictated by the specification of the IP block317 i.

The channel function generator 325 receives and compares the testresponse signals and the test stimulus signals. Any of the test responsesignals that are incorrect are logged to the DRAM 320 through the memorycontroller 360 for further analysis.

The deterministic operation mode of the automated test equipment system300 as described provides the deterministic operation as in theautomated test equipment systems of the prior art. The mode selectioncircuits 340 and 365 switch from the deterministic operation mode to thenon-deterministic operation mode based on the state of the protocolaware selection signal 345. For the deterministic operation mode, asjust described, the protocol aware selection signal 345 is set such thatthe channel function generator 325 controls the transfer of the teststimulus signals from the channel function generator 325. In thenon-deterministic operation mode, control of the source memory 330, andthe capture memory 355 is from a protocol decode circuit 370. Thetransmission of the test stimulus signals is transferred from thechannel function generator 325 to the protocol decode circuit 370.

The protocol decode circuit 370 may be a reconfigurable integratedcircuit such as a field programmable gate array (FPGA) that isconfigured to accept a protocol from the SOC device-under-test 315,decode the protocol into a command, address, and/or data. From thereceived address, command, control, timing, and data, the protocoldecode circuit 370 determines the structure and the timing of the teststimulus signals defined by the specification of the IP block 317 i. Theprotocol decode circuit 370 communicates with the source memory 330which extracts the necessary test stimulus signals from the DRAM 320through the memory controller 360. The test stimulus signals aretransferred through the mode selection circuit 340 from the sourcememory 330 and those test stimulus signals that represent commandresponses to the IP block 317 i are transferred through the modeselection circuit 365. The test stimulus signals are transferred throughthe interconnections 337 and 339 to the pin electronics 310 a and 310 bto the IP block 317 i of the SOC device-under-test 315. For example, ifthe automated test equipment system 300 is to stimulate random accessmemory (RAM) and the IP block 317 i of the SOC device-under-test 315 isa memory controller, the memory controller sends test response signalsthat when decoded are the address, command, control, timing, and datafor a RAM. The protocol decode circuit 370 receives test responsesignals and decodes the test response signals into the address, command,control, timing, and data. The protocol decode circuit 370 determinesthe structure and timing of the test stimulus signals that are to besupplied to the IP block 317 i of the SOC device-under-test 315. In thecase of a read command of the RAM, the protocol decode circuit 370determines the read latency timing and the structure of the data to betransferred and commands the source memory 330 to transfer the teststimulus signals accordingly with the protocol decode circuit 370providing any of the specified command and timing response signals forthe memory controller of the IP block 317 i.

In the case of the write, the protocol decode circuit 370 decodes theaddress and commands the capture memory to store the written data. Theprotocol decode circuit 370 also initiates responses acknowledging thewrite as a test stimulus signal to the IP block 317 i through the modeselection circuit 365, the transmission circuit 335 and the pinelectronics 310 a and 310 b. In this action, any of the IP blocks 317 a,317 b, . . . , and 317 n that are being tested will interact with the IPblock 317 i in a functionally correct manner as though the SOCdevice-under-test 315 were in its standard operating environment.

It should be noted that the source memory 330 and the capture memory 355are ideally a random access memories such as a static RAM or DynamicRAM. However, in simulating the operating environment of a highperformance SOC device-under-test 315, the source memory 330 and thecapture memory 355 may be First-In-First-Out (FIFO) memories. The FIFOmemories by their nature allow faster transfer and receipt of the teststimulus signals than do the Static and Dynamic RAM's. Further, in thisembodiment the source memory 330, the capture memory 355, and the modeselection circuits 340 and 365 are also reconfigurable circuits withinan FPGA.

While this embodiment is shown with a single ATE clock 385 for theprotocol specific circuit 305, the protocol specific circuit 305 mayoptionally be clocked by the Device-Under-Test clock during thenon-deterministic mode of operation and by the automated test equipmentsystem clock 385 during the deterministic mode to assure appropriatesynchronicity of the transfer of the test response signals. An optionalmultiplexer (not shown) similar to the optional multiplexer 275, asshown in FIG. 2, may be provided to switch between the Device-Under-Testclock and the automated test equipment system clock 385. The optionalmultiplexer is controlled by the protocol aware selection signal 345 tocontrol the operational mode of the protocol specific circuit 305between the deterministic and the non-deterministic modes.

The embodiments of FIGS. 2 and 3 of the automated test equipment systemshow a single protocol aware channel that includes the protocol specificcircuit. In conventional automated test equipment system, there aremultiple channels with each channel controlling the stimulus andresponse for a specific number of pins (i.e. 8 pins) of the SOCdevice-under-test. The multiple protocol aware channels of the automatedtest equipment system of some embodiments communicate with otherprotocol aware channels to decode protocol commands from the SOCdevice-under-test and then generate and synchronize the test stimulussignals that are the correctly structured and timed responses expectedby the SOC device-under-test.

Refer now to FIG. 4 for a description of the automated test equipmentsystem 400 of this embodiment. The automated test equipment system 400has multiple channels of the protocol specific circuits 405 a, . . . ,405 n that are connected to multiple pin electronic units 410 a, . . . ,410 n. Each of the multiple pin electronic units 410 a, . . . , 410 n asdescribed above provide the electrical interface 402 a, . . . , 402 nand 404 a, . . . , 404 n between the SOC device-under-test 440 and theautomated test equipment system 400 through the physicalinterconnections of the load adapter. Each of the protocol specificcircuits 405 a, . . . , 405 n is connected to at least one of themultiple pin electronic units 410 a, . . . , 410 n to provide the teststimulus signals to and receive the test response signals from the SOCdevice-under-test 440.

Each of the protocol specific circuits 405 a, . . . , 405 n has aprotocol aware controller 415 which functions as the protocol awareengine 270 of FIG. 2, or the protocol decode circuit 370 of FIG. 3, incoordination with the remaining circuitry of the protocol specificcircuit 205 of FIG. 2 or the protocol specific circuit 305 of FIG. 3.Each protocol aware controller 415 of the protocol specific circuits 405a, . . . , 405 n communicates with its designated DRAM 420 a, . . . ,420 n to provide the necessary test commands and to log the test resultsof the exercising of the SOC device-under-test 440.

In protocols that have a large number of pins, the protocol specificcircuits 405 a, . . . , 405 n coordinate the decoding of the commandsand generate the test response signals that simulate the expectedresponses synchronously. To simulate the expected responsessynchronously, the protocol specific circuits 405 a, . . . , 405 ncommunicate through a synchronization communication interface 425between those of the protocol specific circuits 405 a, . . . , 405 nthat may cooperate. This cooperation may effect the latency of theoperation and thus the communication is structured to minimize theimpact of the cross communication between the protocol specific circuits405 a, . . . , 405 n. For instance one of the protocol aware controllers415 may act as a master and receive the test stimulus signals directlyfrom adjacent protocol specific circuits 405 a, . . . , 405 n fordecoding. The master protocol aware controller 415 then dispatches theappropriate instructions for constructing the structure and timing ofthe test response signals specified by the protocol, while minimized theimpact of the latency for the operation. The latency synchronizationsignal line (ISL) 435 is used by the master protocol aware controller415 for dispatching the initiation of a particular protocol actionacross multiple protocol specific circuits 405 a, . . . , 405 n.

The automated test equipment system 400 may have multiple masteroscillators 430 a and 430 b to generate the different timings determinedby the protocol specific circuits 405 a, . . . , 405 n. This is trueespecially for the deterministic operation of the automated testequipment system 400. In the non-deterministic operation of theautomated test equipment system 400, the master oscillators 430 a and430 b may be used for those portions of the testing involvingdeterministic operation while an exterior timing from the SOCdevice-under-test 440 may be used for the protocol aware controller 415in non-deterministic operation.

Refer now to FIGS. 5 a and 5 b for a description of a method forsimulating within an automatic test system a functional operationalenvironment into which a device-under-test is placed for functionaltesting. The device-under-test is an SOC integrated circuit that isplaced in an adapter (or load) board, i.e. a DIB. The pin electronicsprovides the electrical interface, via the DIB, between thedevice-under-test and the test circuitry of the automatic test system.The method begins by (Box 500) selecting the mode of operation of theautomatic test system. If the deterministic mode of operation isdetermined (Box 505) to be selected, the normal operational testing ofthe SOC DUT is performed (Box 510). If the non-deterministic mode isdetermined (Box 505) to be selected, a non-deterministic response signalis received (Box 515) from the SOC device-under-test. Based on apredetermined protocol, an expected stimulus signal to be transferred tothe SOC DUT is ascertained (Box 520) from the non-deterministic responsesignal. Transmission of the expected stimulus signal from the automatictest system to the device-under-test is initiated (Box 525). Thenon-deterministic response signal is stored (Box 530) within a responsecapture storage device. The non-deterministic response signal isevaluated (Box 540) to determine if the non-deterministic responsesignal was correctly transmitted from the SOC DUT to determine anoperational condition of the SOC DUT.

Expected stimulus signals are generated (Box 545) from an encodedstimulus data and stored (Box 550) in an expected stimulus signalstorage device. At least one of the expected stimulus signals isselected (Box 560). From the decoded non-deterministic response signal,the timing and latency delay of the expected stimulus signal issynchronized (Box 565) for transmission to the SOC DUT.

The predetermined protocols of the non-deterministic response signalsand the expected stimulus signals may be a random access memoryinterface protocol, a communication interface protocol, or computingdevice interface protocol.

The decoding of the non-deterministic response signal permits theautomatic test system to transfer an expected response to the SOC DUT bythe expected stimulus signals with the appropriate timing and latencydelays that would be expected in the normal operating environment of theSOC DUT.

The “JEDEC Standard JESD79-3—DDR3 SDRAM Standard”, JEDEC Solid StateTechnology Association, Arlington, Va., June 2007, defines the DoubleData Rate (DDR3) Synchronous Dynamic Random Access Memory (SDRAM)specification, including features, functionalities, AC and DCcharacteristics, packages, and ball/signal assignments. One of the IPblocks of a SOC DUT, as described above, may be a controller circuit fora memory system containing DDR3 SDRAM. In a functional evaluation of theIP block of the SOC DUT, other IP Blocks may be requesting transfer ofdata between the controller circuit IP block and the memory system. In atest environment this type of access is not deterministic, but is basedon the timing of the interactions between the IP blocks. The controllerIP Block will activate the timing, command, control, and data signals totransfer data between the DDR3 SDRAM and the SOC DUT. The automated testequipment system of various embodiments responds with the appropriatesignals at the specified timings and structure for the controller IPblock to correctly interact with the remaining IP Blocks of the SOC DUT.As noted the timing of this interaction is non deterministic and isaccomplished according to the specifications of the protocol. Referringto FIG. 6, the controller IP block 600 generates the data signals 605 aand 605 b, the command signals (RAS#, CAS#, and WE#) 610, the select andenable signals 615 and 620, the clocking signals (CK and CK#) 625, theaddress signals, 630, and the strobe and synchronizing signals 635 a and635 b as defined in the DDR3 SDRAM Standard.

The protocol aware controller of various embodiments receives thesignals, decodes the action, execute the commands to perform therequested action. The protocol controller then times and synchronizesthe test stimulus signals that simulate the DDR3 SDRAM responses so thatthey arrive at the SOC DUT with a consistent Clock Latency (CL). Thenon-operational (NOP) cycles need to be captured and compared. Thestripping out NOP cycles reduces the data set size used by the automatedtest equipment system of the various embodiments and is one of theimmediate benefits of the protocol aware controller within the automatedtest equipment system of the various embodiments.

As can be seen from this example, the DDR3 SDRAM protocol includes atotal of 26 Address/Command/Clocking pins (610, 615, 620, 625, and 630)and another 22 Data/Mask/Strobe pins (605 a, 605 b, 635 a, and 635 b)that are to be observed. A total of 48 channels are employed within theautomated test equipment system of this embodiment to simulate the DDR3SDRAM function. If each of the protocol aware controllers controls atotal of eight channels, with at least six of the protocol awarecontrollers cooperatively linked to simulate the DDR3 SDRAM to test thefunctional operation of the controller IP block 600.

Refer now to FIG. 7 for a description of the channel structure of theautomated test equipment system 700. The automated test equipment system700 has a number of channel boards 705 a and 705 b (2 in this example).Each of the channel boards 705 a and 705 b has a number (5 in thisexample) of protocol specific circuits 710 a, . . . , 710 e, and 710 f,. . . , 710 j. Each of the protocol specific circuits 710 a, . . . , 710e, and 710 f, . . . , 710 j is capable of decoding, controlling, andsynchronizing a number of input and output signals, in this exampleeight (8). The channel layout for the automated test equipment system700 is designed to accommodate the protocol of the DDR3 SDRAM from theDDR3 SDRAM controller IP block 600. Certain restrictions for theprotocol is observed for these channels of the protocol specificcircuits 710 a, . . . , 710 e, and 710 f, . . . , 710 j that are relatedto tracking. The DDR3 SDRAM timing is specified relative to either thetiming clocks (CK) or the data strobes (DQS), the tracking function ofthe protocol specific circuits 710 a, . . . , 710 e, and 710 f, . . . ,710 j are employed to ensure that the appropriate timing andsynchronization criteria is met. The Address/Command channels 740, 745,750, and 755 will follow the clocking channel 740 and the Data and Maskchannels 725, 730, and 735 will follow their respective data strobe pins725 and 730.

Since the results of the decoded address, command, control, timing, anddata signals of a protocol are communicated between the protocolspecific circuits 710 a, . . . , 710 e, and 710 f, . . . , 710 j, thetracking signals 720 and command signals 715 are connected to transferthe necessary tracking signals between the protocol specific circuits710 a, . . . , 710 e, and 710 f, . . . , 710 j. In the case of the DDR3SDRAM protocol, the clock timing and command signals 740 and the datastrobe (DQS) 725 and 730 are tracked and transferred to the otherprotocol specific circuits 710 a, . . . , 710 e, and 710 f, . . . , 710j.

It should be noted that in most cases all or most of the channels (8) ofthe protocol specific circuits 710 a, . . . , 710 e, and 710 f, . . . ,710 j are used, but in two of the cases, the channels are only partiallyused (7). This is because the tracking function is split on even channelboundaries for the case of tracking a differential signal such as theclock timing (CK) and the data strobe (DQS) signals that are both diffsignals. In each case, the channel boards 705 a and 705 b are designedsuch that the tracked signal is the first in a tracking chain followedby the dependent signals.

It should further be noted that the DDR3 SDRAM protocol spans more thanthe number of protocol specific circuits 710 a, . . . , 710 e, and 710f, . . . , 710 j that populate the channel boards 705 a and 705 b. Thetracking and command signals propagate from one channel board 705 a and705 b to the other channel boards 705 a and 705 b. Backplane interfaceboard signals exist in automated test equipment systems 700 to allow forthis propagation.

One of the protocol specific circuits 710 a, . . . , 710 e, and 710 f, .. . , 710 j is designated as the control protocol specific circuit 710d. The control protocol specific circuit 710 d receives the varioustiming and command signals (CK, CS, CAS, RAS, WE) 740 for the DDR3 SDRAMprotocol. Because of the necessity for decoding the timing and commandsignals (CK, CS, CAS, RAS, WE) 740 appropriately and expeditiously, thetiming and command signals (CK, CS, CAS, RAS, WE) 740 for any protocolare not split between the protocol specific circuits 710 a, 710 e, and710 f, . . . , 710 j.

Three protocol specific circuits 710 f, 710 g, and 710 h are not usedfor this implementation of the DDR3 SDRAM protocol. The three protocolspecific circuits 710 f, 710 g, and 710 h are optionally used to expandthe data bus of the DDR3 SDRAM to 32 bits as opposed to the sixteen bitsof the example. The three protocol specific circuits 710 f, 710 g, and710 h alternately are used as regular channels or used for an entirelydifferent protocol for another of the IP blocks of the SOC DUT.

Refer now to FIGS. 8 and 9 for an examination of the timingcharacteristics of the DDR3 SDRAM Protocol. In FIG. 8 the rising edge800 of clocking signal (CK) occurs in the middle of Command/Addresssignals when their signals are stable and valid. Alternately the risingedge 805 of data strobe signals (DQS) are sent out at the beginning ofdata signal (DQ) transfer time. A tracker or transition detector (notshown) monitoring the clock signals (CK/CK#) permits the offset of thedata strobe (DQS) from the tracker by 90 degrees in order to positionthe level transition of the data strobe (DQS) in the middle of the clocksignal (CK) when the clock signal is not in transition. Additionally onthe Address/Command Control protocol specific circuits, the data strobesare activated at the tracker time or alternately offset one completeclock signal (CK) cycle later in order to center the data strobes (DQS)at the center of the eye of the data signals (DQ). This will permit the“shmooing” or varying of the conditions and inputs of the data strobes(DQS) timings to determine the eye width to find the passing regions.

In the Write Cycle of FIG. 9, when the controller IP block is sourcingdata, the position of data strobe (DQS) moves to the center of the datavalid time 810. The tracking of the data strobes (DQS) allows theplacement of the position of the data strobes (DQS) at the appropriatetimes 810 of the data signals (DQ).

The protocol specific circuits 710 a, . . . , 710 e, and 710 f, . . . ,710 j converts the controller IP block 600 clock phase to the testerclock phase (with the tracker). Some degree of drift between theprotocol specific circuits 710 a, . . . , 710 e, and 710 f, . . . , 710j clock and clocking and data strobe signals (CK and DQS) of thecontroller IP block 600. This allows generation of the clocks on thechannel boards 705 a and 705 b without attempting to use the DDR3 SDRAMcontroller IP block 600 clock directly. The protocol specific circuits710 a, . . . , 710 e, and 710 f, . . . , 710 j will be clocking datain/out of the protocol specific circuits 710 a, . . . , 710 e, and 710f, . . . , 710 j at a slower rate (¼ the DDR3 SDRAM controller IP block600 clock rate), so at least for the DDR3 SDRAM interface, the protocolspecific circuits 710 a, . . . , 710 e, and 710 f, . . . , 710 j clockcould be ¼ the rate of the clock signals (CK) (200 MHz max). To matchthe data rate of the DDR3 SDRAM Standard, the capture memory and thesource memories of the protocol specific circuits 710 a, . . . , 710 e,and 710 f, . . . , 710 j may be paralleled FIFO memory that are read orwritten at the slower rate of the automated test equipment system whileallowing the data to be transferred to the controller IP block 600 ofthe SOC DUT at its operational rate.

The internal clocking of the protocol specific circuits 710 a, . . . ,710 e, and 710 f, . . . , 710 j have two alternatives. One is to use theautomated test equipment system clock to clock protocol specificcircuits 710 a, . . . , 710 e, and 710 f, . . . , 710 j. Alternately,the clocking of the SOC DUT may be used for clocking the protocolspecific circuits 710 a, . . . , 710 e, and 710 f, . . . , 710 j.

All DDR3 SDRAM Standard commands are defined by the state of the commandsignals (CS#, RAS#, CAS#, WE# and CKE) at the rising edge of clocksignal (CK). Each unique command is present on any of the clock signal(CK) boundaries 800. There are limitations, however, on allowablecommand sequences. For example a READ or WRITE with Burst Length 4cannot be interrupted until complete so that there is at least one NOPor DESELECT between consecutive READ/WRITE commands. A complete table ofthese constraints can be found in the DDR3 SDRAM Standard. It isoptional that violations of these constraints be flagged but there is asubset of violations that will cause the protocol specific circuits 710a, . . . , 710 e, and 710 f, . . . , 710 j to operate improperly (READfollowed immediately by another READ for example). These will set anerror flag and be logged as a fault in the controller IP block 600 ofthe SOC DUT.

There are only a limited number of actions the protocol specificcircuits 710 a, . . . , 710 e, and 710 f, . . . , 710 j can perform onany given cycle:

-   -   1. Store (or compare to expected response) the        Address/Command/WR Data into Capture memory;    -   2. Source Read Data from the source memory (READ FIFO); or    -   3. Do nothing.

A lookup table is resident in the DRAM of the protocol specific circuits710 a, . . . , 710 e, and 710 f, . . . , 710 j for converting thecommand signal inputs (CS#, RAS#, CAS#, WE# and CKE) into the possibleactions.

Various embodiments of the automated test equipment system will supportmany different protocols for the different SOC DUT. The correct protocolis configured in the three protocol specific circuits 710 a, . . . , 710f, 710 g, and 710 h when the testing of the SOC DUT is initiated. Theprotocols generally consist of random access memory interface protocols,communication interface protocols, computing device interface protocols,and diagnostic testing protocols, but other protocols are possible.These protocols may fall into two broad categories. In a first example,the SOC DUT controls the bus (bus master). In a second example, theautomated test equipment system controls the bus. The DDR3 SDRAMprotocol, in the example above, is an example where the SOC DUT controlsthe bus and the automated test equipment system responds.

It is significant to note that multiple protocol engines may beimplemented in the intellectual protocol blocks of the SOC DUT. Thus,multiple protocol engines may be running concurrently on the automatictest equipment. For example, there may be a DRAM port, a JTAG port, anda MDIO port protocol engine running concurrently in the automated testequipment.

As described above, in the first example, the SOC device-under-testcontrols the interface between automated test equipment system and theSOC device-under-test. In the second example, the automated testequipment system controls the interface between the SOCdevice-under-test and the automated test equipment system. In the firstexample, the SOC device-under-test communicates the non-deterministicsignals and the automated test equipment system responds. In the secondexample, the automated test equipment system sends the test stimulussignals with the appropriate protocol structure and timing to the SOCdevice-under-test and the SOC device-under-test responds with thenon-deterministic test response signals that are decoded. In eitherexample, the automated test equipment recognizes a non-deterministicresponse signal from the SOC device-under-test and responds.

It should be understood that the above methods and apparatus may beutilized in the manufacture of a device such as component, board, orconsumer electronic good, having a SOC. Thus, after fabricating a SOC,it may be tested by simulating a functional operational environment in atester by receiving a non-deterministic response signal from thesystem-on-a-chip, ascertaining an expected stimulus signal to betransferred to the system-on-a-chip from the non-deterministic responsesignal based on a predetermined protocol, and initiating transmission ofthe expected stimulus signal to the system-on-a-chip, as describedabove. The testing may be performed prior to, or after installing theSOC in the device.

While this invention has been particularly shown and described withreference to the embodiments thereof, it will be understood by thoseskilled in the art that various changes in form and details may be madewithout departing from the spirit and scope of the invention.

1. A protocol specific circuit for simulating a functional operationalenvironment into which a device-under-test is placed for functionaltesting, the protocol specific circuit comprising a protocol awarecircuit constructed to receive at least one non-deterministic signalcommunicated by a device-under-test and to control a transfer of atleast one test stimulus signal to the device-under-test in response tothe at least one non-deterministic signal.
 2. The protocol specificcircuit of claim 1, wherein the protocol aware circuit is constructed tocontrol the transfer of the test stimulus signal by selecting a teststimulus signal response based on the non-deterministic signal from thedevice-under-test and initiating transmission of the selected at leastone test stimulus signal.
 3. The protocol specific circuit of claim 1,wherein the protocol specific circuit is constructed to receive the atleast one non-deterministic signal communicated by a protocol specificdevice-under-test via pin electronics and to control transfer of the atleast one test stimulus signal from a test signal generator to thedevice-under-test.
 4. The protocol specific circuit of claim 3, whereinthe protocol specific circuit is constructed to store the at least onetest stimulus signal from the test signal generator in a stimulus signalstorage device.
 5. The protocol specific circuit of claim 4, wherein thestimulus signal storage device comprises at least one of: a) FIFOmemory; or b) random access memory.
 6. The protocol specific circuit ofclaim 1, wherein the protocol specific circuit is constructed to storethe at least one non-deterministic signal in a response signal storagedevice.
 7. The protocol specific circuit of claim 6, wherein theresponse signal storage device comprises at least one of: a) FIFOmemory; or b) random access memory.
 8. The protocol specific circuit ofclaim 6, wherein the protocol specific circuit is constructed to extractthe at least one non-deterministic signal from the response signalstorage device for comparison by a failure processor with an expectedresponse signal, and determine an operational condition of thedevice-under-test.
 9. The protocol specific circuit of claim 1, whereinthe protocol specific circuit is constructed for mounting in automatedtest equipment to allow the automatic test equipment to simulate afunctional operational environment into which the device-under-test isplaced for functional testing and the protocol aware circuit interpretsthe at least one non-deterministic signal to determine a synchronizationtime and a latency time for transmission of the at least one teststimulus signal.
 10. A protocol specific circuit comprising aconfigurable protocol aware circuit capable of being preconfigured tocommunicate at least one test stimulus signal between a test signalgenerator and a specific device-under-test via pin electronics inresponse to a non-deterministic signal from the device-under-test. 11.The protocol specific circuit of claim 10, wherein the protocol specificcircuit is preconfigured to respond to a specific device-under-test inresponse to the non-deterministic signal comprising an asynchronouslyoccurring signal from the device-under-test.
 12. The protocol specificcircuit of claim 10, wherein the protocol specific circuit comprises aprotocol decoder.
 13. The protocol specific circuit of claim 10, whereinthe protocol specific circuit is programmable.
 14. The protocol specificcircuit of claim 13, wherein the protocol specific circuit comprises afield programmable gate array.
 15. The protocol specific circuit ofclaim 14, wherein the field programmable gate array comprises theprotocol aware circuit and a memory device, the protocol aware circuitbeing coupled to the memory device.
 16. The protocol specific circuit ofclaim 15, wherein the memory device comprises at least one of: a) FIFOmemory; or b) random access memory.
 17. The protocol specific circuit ofclaim 10, wherein the protocol specific circuit comprises a memorybuffer configured to store the at least one test stimulus signalgenerated by the test signal generator and to provide the stored teststimulus signal via the pin electronics, to the device-under-test inresponse to a non-deterministic signal from the device-under-test. 18.The protocol specific circuit of claim 17, wherein the memory buffercomprises at least one of: a) FIFO memory; or b) random access memory.19. The protocol specific circuit of claim 10, wherein the protocolspecific circuit further comprises a pass-through circuit coupled inparallel with the protocol aware for receiving deterministic signalsfrom the device-under-test.
 20. Automated test equipment comprising aprotocol aware channel for testing a device-under-test, the protocolaware channel comprising a protocol specific circuit coupled between atest signal generator and a pin electronics circuit, the protocolspecific circuit being constructed to be capable of being preconfiguredto respond to the protocol specific device-under-test in response to anon-deterministic signal from the device-under-test.
 21. The automatedtester of claim 20, wherein the protocol specific circuit comprises aprotocol decoder.
 22. The automated tester of claim 20, wherein theprotocol specific circuit comprises a field programmable gate array. 23.The automated tester of claim 22, wherein the field programmable gatearray comprises a protocol aware circuit and a memory device, theprotocol aware circuit being coupled to the memory device.
 24. Theautomated tester of claim 20, wherein the protocol specific circuitcomprises a memory buffer configured to store the at least one teststimulus signal generated by the test signal generator and to providethe stored test stimulus signal via the pin electronics, to thedevice-under-test in response to a non-deterministic signal from thedevice-under-test.
 25. The automated tester of claim 20, wherein theprotocol specific circuit further comprises a pass-through circuitcoupled in parallel with a protocol aware circuit for receivingdeterministic signals from the device-under-test.